Pejman Lotfi-Kamran

• Paria Darbani (with Prof. Hakem Beitollahi)

• Ali Ansari (with Prof. Hamid Sarbazi-Azad)
• Mohammad Bakhshalipour (with Prof. Hamid Sarbazi-Azad)
• Farid Samandi (with Prof. Hamid Sarbazi-Azad)

• Divide and Conquer Frontend Bottleneck
  The frontend stalls caused by instruction and BTB misses are a significant source of performance degradation in server processors. Prefetchers are commonly employed to mitigate frontend bottleneck. However, next-line prefetchers, which are available in server processors, are incapable of eliminating a considerable number of L1 instruction misses. Temporal instruction prefetchers, on the other hand, effectively remove most of the instruction and BTB misses but impose significant area overhead. Recently, an old idea of using BTB-directed instruction prefetching is revived to address the limitations of temporal instruction prefetchers. While this approach leads to prefetchers with low area overhead, it requires significant changes to the frontend of a processor. Moreover, as this approach relies on the BTB content for prefetching, BTB misses stall the prefetcher, and likely lead to costly instruction misses. In this work, we divide the frontend bottleneck into three categories and use a divide-and-conquer approach to propose simple and effective solutions for each one. Our proposal, SN4L+Dis+BTB, imposes the same area overhead as the state-of-the-art BTB-directed prefetcher, and at the same time, outperforms it by 5% on average and up to 16%. [ISCA'20] [SRC]
  
  
• Bingo Spatial Data Prefetcher
  To select an access pattern for prefetching, existing spatial prefetchers associate observed access patterns to either a short event with a high probability of recurrence or a long event with a low probability of recurrence. Consequently, the prefetchers either offer low accuracy or lose significant prediction opportunities. In this work, we make a case for associating the observed spatial patterns to both short and long events to achieve high accuracy while not losing prediction opportunities. We propose Bingo spatial data prefetcher in which short and long events are used to select the best access pattern for prefetching. We design Bingo in such a way that just one history table is needed to maintain the association between the access patterns and the long and short events. We show that Bingo improves system performance by 60% over a baseline with no data prefetcher and 11% over the best-performing prior spatial data prefetcher. [HPCA'19]
  
  
• Domino Temporal Data Prefetcher
  While temporal prefetching techniques are effective at reducing the number of data misses, there is a significant gap between what they offer and the opportunity. This work aims to improve the effectiveness of temporal prefetching techniques. We identify the lookup mechanism of existing temporal prefetchers responsible for the large gap between what they offer and the opportunity. Existing lookup mechanisms either not choose the right stream in the history, or unnecessarily delay the stream selection, and hence, miss the opportunity at the beginning of every stream. In this work, we introduce Domino prefetcher that logically looks up the history with both one and two last miss addresses to find a match for prefetching. We show that Domino prefetcher captures more than 90% of the temporal opportunity and offers 16% higher performance over a system with no data prefetcher and 6% over the state-of- the-art temporal data prefetcher. [HPCA'18]
  
  
• Near-Ideal Networks-on-Chip for Servers
  Most of the NOC delay is due to per-hop resource allocation. In this work, we take advantage of proactive resource allocation (PRA) to eliminate per-hop resource allocation time in single-cycle multi-hop networks to reach a near-ideal network for servers. PRA is undertaken during (1) the time interval in which it is known that LLC has the requested data, but the data is not yet ready, and (2) the time interval in which a packet is stalled in a router because the required resources are dedicated to another packet. Through detailed evaluation targeting a 64-core processor and a set of server workloads, we show that our proposal improves system performance by 12% over the state-of-the-art single-cycle multi-hop mesh NOC. [HPCA'17]
  
  
• Neural Accelerators for Graphics Processing Units
  Graphics processing units (GPUs) accelerate the execution of diverse classes of applications, such as recognition, gaming, data analytics, weather prediction, and multimedia. Many of these applications are amenable to approximate execution. This application characteristic provides an opportunity to improve the performance and efficiency of GPUs. We studied the effectiveness of neural approximate acceleration for GPU workloads. We showed that applying CPU neural accelerators to GPUs leads to high area overhead. Therefore, we defined a low overhead neurally accelerated architecture for GPUs that enables scalable integration of neural acceleration on the large number of GPU cores. Our evaluation indicates 2.4× speed up and 2.8× energy reduction with 10% quality loss and less than 1% area overhead. [MICRO'15]
  
  
• Organization of Scale-Out Processors
  I proposed NOC-Out, a many-core organization for Scale-Out Processors that has low area overhead and provides fast access to the last-level cache (LLC) for delivering high performance. While existing many-core organizations offer an uneasy compromise between low area overhead and fast access to the LLC, NOC-Out offers both features simultaneously. The proposed organization is based on one critical observation: there is almost no core-to-core communication in scale-out workloads. Based on this observation, NOC-Out decouples cores and the last-level cache, eliminates all unneeded core-to-core links, and uses specialized core-to-LLC networks to connect cores to the last-level cache and vice versa. [MICRO'12]
  
  
• Scale-Out Processors
  I proposed a methodology for the design of highly efficient many-core processors for scale-out workloads. This research relies on two critical observations with regard to such many-core processors. First, large LLCs waste precious silicon real estate. Second, the organization of a many-core processor has a significant impact on its performance. Existing many-core chips, such as those offered by Tilera, sacrifice much of the on-die real estate to LLC and employ a tiled organization that incurs a high on-chip communication overhead. In contrast, I proposed a many-core processor based on the notion of pods. A pod is a module that tightly couples many cores to a modestly sized LLC through a low-latency interconnect. The proposed processor integrates many pods wherein each pod is a self-contained server-on-a-chip running a full software stack. I formulated a methodology to determine the optimal number of cores and LLC capacity to integrate in a pod for peak throughput. The proposed design, called the Scale-Out Processor, delivers peak throughput in today's process technology and affords near-ideal scalability as the technology scales. [ISCA'12]
  
  
• Area- and Energy-Efficient Coherence Directories for Many-Core CMPs
  We proposed the Cuckoo directory, an energy- and area-efficient scalable directory organization. Existing directory organizations suffer from the lack of energy or area efficiency at high core counts due to wide associative lookups or capacity overprovisioning. Rather than significantly over-provisioning storage capacity to avoid storage conflicts in a traditional lookup table, the Cuckoo directory uses the Cuckoo Hashing algorithm to relocate conflicting entries within the directory to alternate non-conflicting locations. Leveraging the mathematically robust properties of Cuckoo Hashing enables compact and energy-efficient coherence directories with predictable asymptotic behavior. [HPCA'11]
  
  
• Lookup Filtering to Reduce Power Consumption of Coherence Directories
  I proposed the TurboTag filtering mechanism to reduce the energy usage of coherence directories in many-core processors. Coherence directories dissipate a significant fraction of their power on unnecessary lookups when running commercial server and scientific workloads. As coherence enforcement is a known performance bottleneck of multi-threaded software, data sharing in optimized high-performance software is minimal. Consequently, the majority of the accesses to the coherence directory find no sharers in the directory because the data are not available in the on-chip private caches, effectively wasting power on the coherence checks. TurboTag reduces power consumption of coherence directories by filtering (almost all) needless directory lookups. [ISLPED'10]
  
  
• Cost-Effective Globally Aware Dynamic Routing Protocols to Avoid Congestion in NOCs
  I proposed low-cost adaptive routing algorithms for network-wide congestion avoidance. This research enhanced conventional adaptive routings that only rely on local indicators for congestion estimation with low-cost, non-local (global) indicators. [JSA'10]
  
  
• Data Structure for Efficient RT-Level Representation
  Formal verification of microprocessors requires a mechanism for efficient representation and manipulation of both arithmetic and random Boolean functions. State-of-the-art representations can effectively represent arithmetic expressions at the word-level but are not memory efficient in representing bit-level logic expressions. In this research, I presented modifications to the state-of-the-art representations to improve the ability of bit-level logic representation while maintaining robustness in arithmetic word-level representation. [ASP-DAC'05]

• AxBench
• CloudSuite on Simics
• Flexus

• Divide and Conquer Frontend Bottleneck.
  • Barcelona Supercomputing Center (Virtual Talk), January 2021.
  • Institute for Research in Fundamental Sciences (IPM), Tehran, Iran, February 2021.
• Domino Temporal Data Prefetcher.
  • Conference talk at HPCA'18, Vienna, Austria, February 2018.
    
    
• NOC Characteristics of Cloud Applications.
  • Conference talk at CADS'17, Kish Island, Iran, December 2017.
    
    
• Iran's National Grid Initiative: Objectives, Challenges, and Opportunities
  • Conference talk, Russian Supercomputing Days, September 2017.
    
    
• Neural Acceleration for GPU Throughput Processors
  • Institute for Research in Fundamental Sciences, Tehran, Iran, October 2015.
    
    
• Scale-Out Processors.
  Selected talks:
  • Institute for Research in Fundamental Sciences, Tehran, Iran, January 2014.
  • Sharif University of Technology, Tehran, Iran, December 2012.
  • Conference talk, 39th International Symposium on Computer Architecture (ISCA'12), June 2012.
    
    
• NOC-Out: Microarchitecting a Scale-Out Processor.
  • Conference talk at MICRO'12, Vancouver, BC, Canada, December 2012.
    
    
• TurboTag: Lookup Filtering to Reduce Coherence Directory Power.
  • Conference talk at ISLPED'10, Austin, Texas, USA, August 2010.
    
    
• BARP - A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs.
  • Conference talk at DATE'08, Munich, Germany, March 2008.
    
    
• Stall Power Reduction in Pipelined Architecture Processors.
  • Conference talk at VLSID'08, Hyderabad, India, January 2008.

Conference Papers

• Ali Ansari, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  Divide and Conquer Frontend Bottleneck.
  ISCA 2020 (International Symposium on Computer Architecture). [SRC]
  
  
• Mohammad Bakhshalipour, Mehran Shakerinava, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  Bingo Spatial Data Prefetcher.
  HPCA 2019 (International Symposium on High-Performance Computer Architecture).
  
  
• Amir Yazdanbakhsh, Choungki Song, Jacob Sacks, Pejman Lotfi-Kamran, Nam Sung Kim, and Hadi Esmaeilzadeh.
  In-DRAM Near-Data Approximate Acceleration for GPUs.   [ ACM Author-Izer ]
  PACT 2018 (International Conference on Parallel Architectures and Compilation Techniques).
  
  
• Mohammad Bakhshalipour, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  Domino Temporal Data Prefetcher.
  HPCA 2018 (International Symposium on High-Performance Computer Architecture).
  
  
• Pejman Lotfi-Kamran, Mehdi Modarressi, and Hamid Sarbazi-Azad.
  NOC Characteristics of Cloud Applications.
  CADS 2017 (International Symposium on Computer Architecture & Digital Systems).
  
  
• Pejman Lotfi-Kamran, Mehdi Modarressi, and Hamid Sarbazi-Azad.
  Near-Ideal Networks-on-Chip for Servers.
  HPCA 2017 (International Symposium on High-Performance Computer Architecture).
  
  
• Amir Yazdanbakhsh, Jongse Park, Hardik Sharma, Pejman Lotfi-Kamran, and Hadi Esmaeilzadeh.
  Neural Acceleration for GPU Throughput Processors.   [ ACM Author-Izer ]
  MICRO 2015 (International Symposium on Microarchitecture).
  
  
• Pejman Lotfi-Kamran, Boris Grot, and Babak Falsafi.
  NOC-Out: Microarchitecting a Scale-Out Processor.
  MICRO 2012 (International Symposium on Microarchitecture).
  
  
• Pejman Lotfi-Kamran, Boris Grot, Michael Ferdman, Stavros Volos, Onur Kocberber, Javier Picorel, Almutaz Adileh, Djordje Jevdjic, Sachin Idgunji, Emre Ozer, and Babak Falsafi.
  Scale-Out Processors.
  ISCA 2012 (International Symposium on Computer Architecture).
  
  
• Michael Ferdman, Pejman Lotfi-Kamran, Ken Balet, and Babak Falsafi.
  Cuckoo Directory: A Scalable Directory for Many-Core Systems.
  HPCA 2011 (International Symposium on High-Performance Computer Architecture).
  Selected by the program committee for the best student paper session.
  
  
• Pejman Lotfi-Kamran, Michael Ferdman, Daniel Crisan, and Babak Falsafi.
  TurboTag: Lookup Filtering to Reduce Coherence Directory Power.   [ ACM Author-Izer ]
  ISLPED 2010 (International Symposium on Low Power Electronics and Design).
  
  
• Pejman Lotfi-Kamran, Masoud Daneshtalab, Caro Lucas, and Zainalabedin Navabi.
  BARP-A Dynamic Routing Protocol for Balanced Distribution of Traffic in NoCs.   [ ACM Author-Izer ]
  DATE 2008 (Design Automation and Test in Europe).
  
  
• Pejman Lotfi-Kamran, Ali-Asghar Salehpour, Amir-Mohammad Rahmani, Ali Afzali-Kusha, and Zainalabedin Navabi.
  Stall Power Reduction in Pipelined Architecture Processors.
  VLSID 2008 (International Conference on VLSI Design).
  
  
• Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, and Zainalabedin Navabi.
  TED+: A Data Structure for Microprocessor Verification.   [ ACM Author-Izer ]
  ASP-DAC 2005 (Asia and South Pacific Design Automation Conference).

Journal Papers

• Fatemeh Golshan, Mohammad Bakhshalipour, Mehran Shakerinava, Ali Ansari, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  Harnessing Pairwise-Correlating Data Prefetching with Runahead Metadata.
  IEEE Computer Architecture Letters 2020.
  
  
• Ali Ansari, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  Code Layout Optimization for Near-Ideal Instruction Cache.
  IEEE Computer Architecture Letters 2019.
  
  
• Mohammad Bakhshalipour, Seyedali Tabaeiaghdaei, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  Evaluation of Hardware Data Prefetchers on Server Processors.   [ ACM Author-Izer ]
  ACM Computing Surveys 2019.
  
  
• Mohammad Bakhshalipour, Aydin Faraji, Seyed Armin Vakil Ghahani, Farid Samandi, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  Reducing Writebacks Through In-Cache Displacement.   [ ACM Author-Izer ]
  ACM Transactions on Design Automation of Electronic Systems 2019.
  
  
• Mohammad Bakhshalipour, Pejman Lotfi-Kamran, Abbas Mazloumi, Farid Samandi, Mahmood Naderan-Tahan, Mehdi Modarresi, and Hamid Sarbazi-Azad.
  Fast Data Delivery for Many-Core Processors.
  IEEE Transactions on Computers 2018.
  
  
• Armin Vakil-Ghahani, Sara Mahdizadeh-Shahri, Mohammad-Reza Lotfi-Namin, Mohammad Bakhshalipour, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  Cache Replacement Policy based on Expected Hit Count.
  IEEE Computer Architecture Letters 2018.
  
  
• Mohammad Bakhshalipour, Pejman Lotfi-Kamran, and Hamid Sarbazi-Azad.
  An Efficient Temporal Data Prefetcher for L1 Caches.
  IEEE Computer Architecture Letters 2017.
  
  
• Amir Yazdanbakhshi, Divya Mahajan, Pejman Lotfi-Kamran, and Hadi Esmaeilzadeh.
  AxBench: A Multiplatform Benchmark Suite for Approximate Computing.
  IEEE Design & Test 2017.
  
  
• Seyyed Hossein Seyyedaghaei Rezaei, Abbas Mazloumi, Mehdi Modarressi, and Pejman Lotfi-Kamran.
  Dynamic Resource Sharing for High-Performance 3-D Networks-on-Chip.
  IEEE Computer Architecture Letters 2016.
  
  
• Pejman Lotfi-Kamran, Mehdi Modarressi, and Hamid Sarbazi-Azad.
  An Efficient Hybrid-Switched Network-on-Chip for Chip Multiprocessors.
  IEEE Transactions on Computers 2016.
  
  
• Pejman Lotfi-Kamran.
  Per-Packet Global Congestion Estimation for Fast Packet Delivery in Networks-on-Chip.
  The Journal of Supercomputing 2015.
  
  
• Boris Grot, Damien Hardy, Pejman Lotfi-Kamran, Babak Falsafi, Chrysostomos Nicopoulos, and Yiannakis Sazeides.
  Optimizing Data-Center TCO with Scale-Out Processors.
  IEEE MICRO 2012.
  
  
• Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Masoud Daneshtalab, Ali Afzali-Kusha, and Zainalabedin Navabi.
  EDXY - A Low Cost Congestion-Aware Routing Algorithm for Network-on-Chips.
  Elsevier Journal of Systems Architecture 2010.
  
  
• Mohammad Hosseinabady, Pejman Lotfi-Kamran, Fabrizio Lombardi, and Zainalabedin Navabi.
  Low Overhead DFT Using CDFG by Modifying Controller.
  IET Computers & Digital Techniques 2007.
  
  
• Mohammad Hosseinabady, Pejman Lotfi-Kamran, and Zainalabedin Navabi.
  Low Test Application Time Resource Binding for Behavioral Synthesis.   [ ACM Author-Izer ]
  ACM Transactions on Design Automation of Electronic Systems 2007.
  
  
• Pejman Lotfi-Kamran and Zainalabedin Navabi.
  Improving Logic-Level Representation of Taylor Expansion Diagram Using Attributed Edges.
  Iranian Journal of Science and Technology 2006.

Book Chapters

• Pejman Lotfi-Kamran and Hamid Sarbazi-Azad.
  Dark Silicon and the History of Computing.
  Chapter 1, Advances in Computers: Dark Silicon and Future On-chip Systems, vol. 110, Elsevier Inc.
  
  
• Amir Yazdanbakhsh, Jongse Park, Hardik Sharma, Pejman Lotfi-Kamran, and Hadi Esmaeilzadeh.
  Accelerating GPU Accelerators Through Neural Algorithmic Transformation.
  Chapter 16, Advances in GPU Research and Practice, Elsevier Inc.
  
  

Workshop Papers

• Majid Dashtbani, Pejman Lotfi-Kamran, Dara Rahmati, Saeid Gorgin, and Hamid Sarbazi-Azad.
  Iran's National Grid Initiative: Objectives, Challenges, and Opportunities.
  Russian Supercomputing Days 2017.
  
  

Theses

• Pejman Lotfi-Kamran.
  Scale-Out Processors.
  Ph.D. dissertation, 2013.
  
  
• Pejman Lotfi-Kamran.
  An Efficient Data Structure for RTL Representation.
  Masters thesis, 2005.

• CE237 Advanced Multiprocessor Architecture at Iran University of Science and Technology (Fall 2018, Spring 2020, Spring 2021)
• CE723 Advanced Computer Architecture at Iran University of Science and Technology (Fall 2020)
• CE723 Advanced Computer Architecture at Sharif University of Technology (Spring 2014-Fall 2014, Spring 2016-Fall 2016)
• CE323 Introduction to Computer Architecture at Sharif University of Technology (Spring 2015, Spring 2016)
• CE722 Advanced Microarchitecture at Sharif University of Technology (Fall 2015)
• ECE061 Discrete Mathematical Structures at University of Tehran (Spring 2007-Spring 2008)

• CS471 Advanced Multiprocessor Architecture at EPFL (Fall 2009 and Fall 2012)
• CS198 Information Technology Project at EPFL (Fall 2011)
• ECE367 Digital Logic Circuits at University of Tehran (Spring 2004-Spring 2005)
• ECE354 Telecommunications 1 at University of Tehran (Fall 2003-Spring 2004)

• 2017 CADS Best Paper Award
• 2016 Young Faculty Award from Iran's National Elites Foundation
• 2012-2013 Intel Ph.D. Fellowship Award
• 2012 HiPEAC Paper Award
• 2011 HiPEAC Paper Award
• 2011 HPCA Best Student Paper Finalist
• 2005 Dean's Honored Graduate
  (Ranked 1st among graduates of the 2005 class)
• 2005 ICEE Best Paper Award
• 2002 Dean's Honored Graduate
  (Ranked 2nd among graduates of the 2002 class)
• 2001 Faculty of Engineering (FOE) Award
  (Awarded annually to the top three students in each track by College of Engineering)

• Playing table tennis and soccer
• Traveling
• Reading (algorithms, computational complexity, etc.)