Last Update:

08/11/18

Amir Mahdi Hosseini Monazzah

 

Post-doc Researcher

School of Computer Science

Institute for Research in Fundamental Sciences

IPM

Tehran, Iran

NORTHERN VIEW OF DEPENDABLE SYSTEM LABORATORY

SHARIF UNIVERSITY OF TECHNOLOGY

FALL 2015

Biography

Amir Mahdi Hosseini Monazzah received the B.Sc. degree in computer engineering from Islamic Azad University (South Tehran branch), Tehran, Iran, in 2009, and the M.Sc. and Ph.D degrees in computer engineering from the Sharif University of Technology, Tehran, Iran, in 2012 and 2017, respectively. As a post-doc fellow he is currently with the school of computer science, institute for research in fundamental sciences (IPM), Tehran, Iran. He has been a member of the Dependable Systems Laboratory since 2010. As a Visiting Researcher, he was with the Embedded Systems Laboratory, University of California, Irvine, CA, USA from 2016 to 2017. His research interests include investigating the reliability challenges of emerging non-volatile memories, fault-tolerant hybrid memory hierarchy design, designing reliable software for unreliable hardware, designing dependable embedded systems, and reliability challenges in multi-core systems.

Teaching

B.S. Courses

 

  • Digital Design, Lecturer, Iran University of Science and Technology, Tehran, Iran.
  • Digital Design Laboratory, Instructor, Sharif University of Technology, Tehran, Iran.

 

    • Under Supervision of: Dr. Hossein Asadi

 

  • Computer Architecture Laboratory, Instructor, Sharif University of Technology, Tehran, Iran.

 

    • Under Supervision of: Dr. Hossein Asadi

 

 

 

M.Sc. Courses

 

  • Fault-Tolerant System Design, Teacher Assistant, Sharif University of Technology, Tehran, Iran

 

    • Under Supervision of: Prof. Seyed Ghassem Miremadi

 

  • Advanced Fault-Tolerant System Design, Teacher Assistant, Sharif University of Technology, Tehran, Iran

 

    • Under Supervision of: Prof. Seyed Ghassem Miremadi

Publications

Journals:

 

  1.  A. M. H. Monazzah, H. Farbeh, and S. G. Miremadi, “OPTIMAS: Overwrite Purging Through In-execution Memory Address Snooping to Improve Lifetime of NVM-based Scratchpad Memories,” Accepted for publication in IEEE Transactions on Device and Materials Reliability (TDMR'17).
  2. Z. Azad, H. Farbeh, A. M. H. Monazzah, and A. G. Miremadi, “AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches,” Accepted for publication in IEEE Transactions on Emerging Topics in Computing (TETC'17).
  3. Z. Azad, H. Farbeh, A. M. H. Monazzah, and A. G. Miremadi, “An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors,” Accepted for publication in IEEE Transactions on Parallel and Distributed Systems (TPDS'16), vol. 28, no. 6, pp. 1564-1577, June 2017.
  4.  A. M. H. Monazzah, H. Farbeh, and S. G. Miremadi, “LER: Least Error Rate Replacement Algorithm for Emerging STT-RAM Caches,” IEEE Transactions on Device and Materials Reliability (TDMR'16), vol. 16, no. 2, pp. 220-226, June 2016.

 

Conferences:

 

  1. B. Donyanavard, A. M. H. Monazzah, T. Muck and N. Dutt, "Exploring Hybrid Memory Caches in Chip Multiprocessors," in Proceedings of IEEE the International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'18), Lille, France, July 9-11, 2018.
  2. B. Safaei, A. M. H. Monazzah, Taha Shahroodi, and A. Ejlali, “Objective Function: A Key Contributor in Internet of Things Primitive Properties,” in Proceedings of The CSI International Symposium on Real-Time and Embedded Systems and Technologies  (RTEST’18), Tehran, Iran, May 9-10, 2018.
  3. G. Ghasemi, A. M. H. Monazzah, and H. Farbeh, "RI-COTS: Trading Performance for Reliability Improvements in Commercial of the Shelf Systems," in Proceedings of IEEE International Symposium on Computer Architecture and Digital Systems (CADS'17), Kish Island, Iran, December 21-22, 2017.
  4. B. Safaei, A. M. H. Monazzah, M. B. Bafroei, and A. Ejlali, “Reliability Side-Effects in Internet of Things Application Layer Protocols,” in Proceedings of IEEE International Conference on System Reliability and Safety  (ICSRS’17), Milan, Italy, December 20-22, 2017.
  5. Z. Azad, H. Farbeh, and A. M. H. Monazzah, “ORIENT: Organized Interleaved ECCs for New STT-RAM Caches,” to appear in Proceedings of IEEE International Symposium on Design, Automation, and Test in Europe (DATE’18), Dresden, Germany, March 19-23, 2017.
  6. G. Ghasemi, A. M. H. Monazzah, and Hamed Farbeh, “RI-COTS: Trading Performance for Reliability Improvements in Commercial Of The Shelf Systems,”  to appear in Proceedings of IEEE International Symposium on Computer Architecture & Digital Systems  (CADS’17), Kish Island, Iran, December 21-22, 2017.
  7.  A. M. H. Monazzah, H. Farbeh, and S. G. Miremadi, “Investigating the Effects of Process Variations and System Workloads on Endurance of Non-Volatile Caches,”  to appear in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’17), Cambridge, United Kingdom, October 23-25, 2017.
  8. B. Donyanavard, A. M. H. Monazzah, T. Muck and N. Dutt, "Work-in-Progress: Exploring Fast and Slow Memories in HMP Core Types," in Proceedings of IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'17), Seoul, South Korea, October 15-20, 2017.
  9.  A. M. H. Monazzah, M. Shoushtari, S. G. Miremadi, A. M. Rahmani, and  N. Dutt, "QuARK: Quality-configurable Approximate STT-MRAM Cache by Fine-grained Tuning of Reliability-Energy Knobs ," in Proceedings of  IEEE  proceedings of International Symposium on Low Power Electronics and Designe (ISLPED'17), Taipei, Taiwan, July 24-26, 2017.
  10. S. Asadi, A. M. H. Monazzah,  H. Farbeh, and S. G. Miremadi, “WIPE: Wearout-Informed Pattern Elimination to Improve the Endurance of NVM-based Caches,” in Proceedings of the IEEE Asia and South Pacific Design Automation Conference (ASP-DAC'17), Tokyo, Japan,  January 16-19, 2017.
  11. E. Cheshmikhani, A. M. H. Monazzah,  H. Farbeh, and S. G. Miremadi, “Investigating the Effects of Process Variations and System Workloads on Reliability of STT-RAM Caches,”  to appear in Proceedings of the IEEE European Dependable Computing Conference (EDCC'16), Gothenburg, Sweden, September 5-9, 2016.
  12. S. G. Ghaemi, A. M. H. Monazzah,  H. Farbeh, and S. G. Miremadi, “LATED: Lifetime-Aware Tag for Enduring Design,”  in Proceedings of the IEEE European Dependable Computing Conference (EDCC'15), Paris, France, September 7-11, 2015.
  13. H. Sayadi, H. Farbeh, A. M. H. Monazzah, and S. G. Miremadi, “A Data Recomputation Approach for Reliability Improvement of Scratchpad Memory in Embedded Systems,”  in Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’14), Amsterdam, Netherlands, October 1-3, 2014.
  14. H. M. Makrani, A. M. H. Monazzah,  H. Farbeh, and S. G. Miremadi, “Evaluation of Sofware-Based Fault-Tolerant Techniques on Embedded OS’s Components,”  in Proceedings of the International Conference on Dependability (DEPEND'14), Lisbon, Portugal, November 16-20, 2014.
  15.  A. M. H. Monazzah, H. Farbeh, S. G. Miremadi, M. Fazeli, and H. Asadi, “FTSPM: A Fault-Tolerant ScratchPad Memory,”  in Proceedings of the Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN’13), Budapest, Hungary, June 24-27, 2013.

Contact

Room 28

 

School of Computer Science

 

Institute for Research in Fundamental Sciences (IPM)

 

No. 70, Lavasani Avenue

 

Tehran, Iran

 

P.O. Box 11155-11365

 

Email: monazzah (at) ipm.ir

 

Telephone: +98 (21) 24509428

 

Fax: +98 (21) 22825454