Day 1: September 23^rd, 2010

09:00-09:30

Opening

09:30-10:30

Keynote 1: Sustainable Digital Infrastructure

Massoud Pedram (University of Southern California)

10:30-11:00

Break

11:00-13:00

Arithmetic Session

Posibits, Negabits, and Their Mixed Use in Efficient Realization of Arithmetic Algorithms
Ghassem Jaberipur and Behrooz Parhami

Optimization and Evaluation of the Reconfigurable Grid Alu Processor (GAP)
Basher Shehan, Ralf Jahr, Sascha Uhrig and Theo Ungerer

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m) using Dual Bases
Hafizur Rahaman, Jimson Mathew, Abu Jabir and Dhiraj K. Pradhan

M-ary Parallel Modular Exponentiation: Software vs. Hardware
Nadia Nedjah, Sérgio Raposo, Marcos Santana and Luiza de Macedo Mourelle

13:00-14:00

Lunch break

14:00-15:00

Keynote 2: Designing many-core platforms for silicon-efficient embedded multimedia computing

Luca Benini (Università di Bologna & STMicroelectronics)

15:00-17:00

SoCs & NoCs Session  

Variation-Aware Task Scheduling and Power Mode Selection for MPSoC Power Optimization
Mahmoud Momtazpour, Maziar Goudarzi and Esmaeel Sanaei

A High-Performance Interlayer Bus Architecture for Three Dimensional Network-on-Chips
Masoud Daneshtalab, Masoumeh Ebrahimi and Hannu Tenhunen

Dynamic Voltage Scaling for Fully Asynchronous NoCs Using FIFO Threshold Levels
Abbas Rahimi and Mostafa Salehi

Proportionally Fair Buffer Allocation in Optical Chip Multiprocessors via Convex Optimization
Mohammad Sadegh Talebi, Hessam Mirsadeghi, Ahmad Khonsari and Mohamed Ould-Khaoua

17:00-17:30

Break & Poster presentation of short papers 1

16-bit Floating Point Math Unit for DSP Applications
Farhad Merchant and Gyana Ranjan Sahoo

A Modulo 2^ n +1 Multiplier with Double-LSB Encoding of Residues
Ghassem Jaberipur and Hanie Alavi

A Novel Error Detection Mechanism for Digital Circuits Using Markov Random Field Modelling
Jahanzeb Anwer

Reduction of Soft Error Effects on a MIPS-based Dual-Core
Moslem Didehban, Saman Khoshbakht, Hamid Zarandi and Saadat Pourmozaffari

Analysis of the Soft Error Effects on CAN Network Controller
Saman Khoshbakht and Hamid Zarandi

A New Compression Ratio Prediction Algorithm for Hardware Implementation of LZW Data Compression
Alireza Yazdanpanah and Mahmoud Reza Hashemi

Power-Area-Delay Efficient Modulo 2n-1 Multiplier for Multiply-Accumulate Unit
Somayeh Timarchi and Mahmood Fazlali

17:30-18:30

Wireless Network Architecture Session

High Throughput Low Power CCMP Architecture for Very High Speed Wireless LANs
Seyyed Alireza Hoseini, Nasser Yazdani, Behnam Khodabandehloo, Mahdi Jelodari Mamaghani and Peyman Teymoori

Remaining-Energy Based Routing Protocol for Wireless Sensor Networks
Millad Ghane and Amir Rajabzadeh

Poster presentation of short papers 1

16-bit Floating Point Math Unit for DSP Applications
Farhad Merchant and Gyana Ranjan Sahoo

A Modulo 2^ n +1 Multiplier with Double-LSB Encoding of Residues
Ghassem Jaberipur and Hanie Alavi

A Novel Error Detection Mechanism for Digital Circuits Using Markov Random Field Modelling
Jahanzeb Anwer

Reduction of Soft Error Effects on a MIPS-based Dual-Core
Moslem Didehban, Saman Khoshbakht, Hamid Zarandi and Saadat Pourmozaffari

Analysis of the Soft Error Effects on CAN Network Controller
Saman Khoshbakht and Hamid Zarandi

A New Compression Ratio Prediction Algorithm for Hardware Implementation of LZW Data Compression
Alireza Yazdanpanah and Mahmoud Reza Hashemi

Power-Area-Delay Efficient Modulo 2n-1 Multiplier for Multiply-Accumulate Unit
Somayeh Timarchi and Mahmood Fazlali

19:00-21:00

Social event & Conference dinner

Day 2: September 24^th, 2010

09:00-11:00

Reliability Session

Dynamic Fault-Tolerant Wormhole Routing in 2-D Meshes
Ali Mortazavi and Farshad Safaei

OTRU: A Non-Associative and High Speed Public Key Cryptosystem
Ehsan Malekian and Ali Zakerolhosseini

Using Input-to-Output Masking for System-Level Vulnerability Estimation in High-Performance Processors
Alireza Haghdoost, Hossein Asadi and Amirali Baniasadi

127. CCDA: Correcting Control-flow and Data Errors Automatically
Mohammad Maghsoudloo, Navid Khoshavi and Hamid Reza Zarandi

11:00-11:30

Break & Poster presentation of short papers 2

11:30-13:00

VLSI Design Session

Chip Master Planning: An Efficient Methodology to Improve Design Closure and Complexity Management of Ultra Large Chips
Ali Jahanian and Morteza Saheb Zamani

On the Design of a New Low-Power CMOS Standard Ternary Logic Gate
Akbar Doostaregan, Mohammad Hossein Moaiyeri, Keivan Navi and Omid Hashemipour

Latency Optimizing Overlay Network For Partitioning Mesh Network-on-Chips Into Multi-Die Systems
Stephen Burgess, Tapani Ahonen and Jari Nurmi

13:00-14:00

Lunch break

13:30-15:00

Router Architecture Session

A Quad Router Design for Next-Generation
Hananeh Aliee and Hamid Reza Zarandi

Universal on-Chip Communication Channel
Mohammad Ali Rahimian and Siamak Mohammadi

Congestion-Aware Network-on-Chip Router Architecture
Chifeng Wang, Wen-Hsiang Hu and Nader Bagherzadeh

15:00-16:00

Keynote 3: Towards energy-scalable data centers

Babak Falsafi (EPFL & Carnegie Mellon University)

16:00-16:30

Break & Poster presentation of short papers 2

SET and SEU Effects on a PLASMA Processor Assessment
Farhad Mohammadian, Ashkan Eghbal, Saadat Pour Mozafari and Hamid.R. Zarandi

Partitioning Methods for Unicast/Multicast Traffic in 3D NoC Architecture
Masoumeh Ebrahimi, Masoud Daneshtalab and Hannu Tenhunen

Exploring a Low-Cost Inter-layer Communication Scheme for 3D Networks-on-Chip
Amir-mohammad Rahmani, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen

Parallel Quick Sort using Shared Memory Architecture
Anukul Chandra Panda and Banshidhar Majhi

Separating Conflict Misses to Reduce Miss-Rate of Caches through an Unified Replacement Policy
Hamed Azimi and Abbas Vafaei

Hardware-based Reliability Tree (HRT) for Fault Tree Analysis
Amir Rajabzadeh and Mohammad Saeed Jahangiry

Achieving Fault Tolerance in Network on Chip(NoC) by Application Remapping
Xiaohang Wang and Shahram Latifi

16:30-17:00

Closing