From 82 papers submitted to CADS2010, 20 papers were qualified and accepted
as regular papers for oral presentation, resulting in a 24% acceptance rate.
Some papers were accepted as short papers for poster presentation at
CADS2010.
Authors of ALL accepted papers (regular and short), registered and presented
at CADS2010, will be contacted to extend their papers and submit them to the
special issues arranged.
|
Regular Accepted |
| ID |
Autors |
Title |
| 5 |
Ghassem Jaberipur and Behrooz Parhami |
Posibits, Negabits, and Their Mixed Use in Efficient Realization of Arithmetic Algorithms |
| 6 |
Basher Shehan, Ralf Jahr, Sascha Uhrig and Theo Ungerer |
Optimization and Evaluation of the Reconfigurable Grid Alu Processor (GAP) |
| 60 |
Ali Mortazavi and Farshad Safaei |
Dynamic Fault-Tolerant Wormhole Routing in 2-D Meshes |
| 65 |
Seyyed Alireza Hoseini, Nasser Yazdani, Behnam Khodabandehloo,
Mahdi Jelodari Mamaghani and Peyman Teymoori |
High Throughput Low Power CCMP Architecture for Very High Speed Wireless LANs |
| 82 |
Mahmoud Momtazpour, Maziar Goudarzi and Esmaeel Sanaei |
Variation-Aware Task Scheduling and Power Mode Selection for MPSoC Power Optimization |
| 83 |
Hananeh Aliee and Hamid Reza Zarandi |
A Quad Router Design for Next-Generation CMPs |
| 86 |
Masoud Daneshtalab, Masoumeh Ebrahimi and Hannu Tenhunen |
A High-Performance Interlayer Bus Architecture for Three Dimensional Network-on-Chips |
| 91 |
Ehsan Malekian and Ali Zakerolhosseini |
OTRU: A Non-Associative and High Speed Public Key Cryptosystem |
| 93 |
Hafizur Rahaman, Jimson Mathew, Abu Jabir and Dhiraj K. Pradhan |
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2m) using Dual Bases |
| 94 |
Ali Jahanian and Morteza Saheb Zamani |
Chip Master Planning: An Efficient Methodology to Improve
Design Closure and Complexity Management of Ultra Large Chips |
| 95 |
Akbar Doostaregan, Mohammad Hossein Moaiyeri, Keivan Navi and Omid Hashemipour |
On the Design of a New Low-Power CMOS Standard Ternary Logic Gate |
| 107 |
Abbas Rahimi and Mostafa Salehi |
Dynamic Voltage Scaling for Fully Asynchronous NoCs Using FIFO Threshold Levels |
| 113 |
Alireza Haghdoost, Hossein Asadi and Amirali Baniasadi |
Using Input-to-Output Masking for System-Level Vulnerability Estimation in High-Performance Processors |
| 117 |
Stephen Burgess, Tapani Ahonen and Jari Nurmi |
Latency Optimizing Overlay Network For Partitioning Mesh Network-on-Chips Into Multi-Die Systems |
| 119 |
Mohammad Sadegh Talebi, Hessam Mirsadeghi, Ahmad Khonsari and Mohamed Ould-Khaoua |
Proportionally Fair Buffer Allocation in Optical Chip Multiprocessors via Convex Optimization |
| 122 |
Millad Ghane and Amir Rajabzadeh |
Remaining-Energy Based Routing Protocol for Wireless Sensor Networks |
| 123 |
Nadia Nedjah, Sérgio Raposo, Marcos Santana and Luiza de Macedo Mourelle |
M-ary Parallel Modular Exponentiation: Software vs. Hardware |
| 127 |
Mohammad Maghsoudloo, Navid Khoshavi and Hamid Reza Zarandi |
CCDA: Correcting Control-flow and Data Errors Automatically |
| 129 |
Mohammad Ali Rahimian and Siamak Mohammadi |
Universal on-Chip Communication Channel |
| 130 |
Chifeng Wang, Wen-Hsiang Hu and Nader Bagherzadeh |
Congestion-Aware Network-on-Chip Router Architecture |
|
Poster Accepted |
| ID |
Autors |
Title |
| 3 |
Farhad Merchant and Gyana Ranjan Sahoo |
16-bit Floating Point Math Unit for DSP Applications |
| 7 |
Ghassem Jaberipur and Hanie Alavi |
A Modulo 2^ n +1 Multiplier with Double-LSB Encoding of Residues |
| 64 |
Jahanzeb Anwer |
A Novel Error Detection Mechanism for Digital Circuits Using Markov
Random Field Modelling |
| 69 |
Moslem Didehban, Saman Khoshbakht, Hamid Zarandi
and Saadat Pourmozaffari |
Reduction of Soft Error Effects on a MIPS-based Dual-Core |
| 70 |
Saman Khoshbakht and Hamid Zarandi |
Analysis of the Soft Error Effects on CAN Network Controller |
| 72 |
Alireza Yazdanpanah and Mahmoud Reza Hashemi |
A New Compression Ratio Prediction Algorithm for Hardware Implementation of
LZW Data Compression |
| 76 |
Somayeh Timarchi and Mahmood Fazlali |
Power-Area-Delay Efficient Modulo 2n-1 Multiplier for Multiply-Accumulate Unit |
| 87 |
Farhad Mohammadian, Ashkan Eghbal,
Saadat Pour Mozafari and Hamid.R. Zarandi |
SET and SEU Effects on a PLASMA Processor Assessment |
| 88 |
Masoumeh Ebrahimi, Masoud Daneshtalab and Hannu Tenhunen |
Partitioning Methods for Unicast/Multicast Traffic in 3D NoC Architecture |
| 102 |
Amir-mohammad Rahmani, Pasi Liljeberg, Juha Plosila and Hannu Tenhunen |
Exploring a Low-Cost Inter-layer Communication Scheme for 3D Networks-on-Chip |
| 115 |
Anukul Chandra Panda and Banshidhar Majhi |
Parallel Quick Sort using Shared Memory Architecture |
| 121 |
Hamed Azimi and abbas vafaei |
Separating Conflict Misses to Reduce Miss-Rate of Caches through an
Unified Replacement Policy |
| 126 |
Amir Rajabzadeh and Mohammad Saeed Jahangiry |
Hardware-based Reliability Tree (HRT) for Fault Tree Analysis |
| 128 |
Xiaohang Wang and Shahram Latifi |
Achieving Fault Tolerance in Network on Chip(NoC) by Application Remapping |
