Keynotes

Wednesday, June 10: Real-Time and IoT – Why and How?

Prof. Lothar Thiele
Swiss Federal Institute of Technology Zurich
Computer Engineering and Networks Laboratory

Prof. Lothar Thiele is a Professor of Computer Engineering at Swiss Federal Institute of Technology Zurich. His research interests include models, methods and software tools for the design of embedded systems, internet of things, cyber-physical systems, sensor networks, embedded software and bioinspired optimization techniques.

Lothar Thiele is associate editor of INTEGRATION – the VLSI Journal, Journal of Signal Processing Systems, IEEE Transaction on Industrial Informatics, Journal of Systems Architecture, IEEE Transactions on Evolutionary Computation, Journal of Real-Time Systems, ACM Transactions on Sensor Networks, ACM Transactions on Cyber-physical Systems, and ACM Transaction on Internet of Things.

In 1986 he received the “Dissertation Award” of the Technical University of Munich, in 1987, the “Outstanding Young Author Award” of the IEEE Circuits and Systems Society, in 1988, the Browder J. Thompson Memorial Award of the IEEE, and in 2000-2001, the “IBM Faculty Partnership Award”. In 2004, he joined the German Academy of Sciences Leopoldina. In 2005, he was the recipient of the Honorary Blaise Pascal Chair of University Leiden, The Netherlands. Since 2010, he is a member of the Academia Europaea. In 2013, he joined the National Research Council of the Swiss National Science Foundation SNF. Lothar Thiele received the “EDAA Lifetime Achievement Award” in 2015. Since 2017, Lothar Thiele is Associate Vice President of ETH for Digital Transformation. In 2019, he joined the Foundation Board of Technopark Zurich as president.

Abstract: If visions and forecasts of industry come true then billions of interconnected embedded devices will soon surround us. We have the legitimate expectation that the individual devices as well as the overall system behaves in a reliable and predictable manner. We expect correct and timely results from sensing, computation, communication and actuation due to economic importance or even catastrophic consequences if the overall system is not working correctly. It will be argued that one of the major reasons for unpredictable and unwanted behavior of IoT systems is due to interference from external or internal processes. We need novel architectural concepts, an associated design process and validation strategies to satisfy the strongly conflicting requirements and associated design challenges of platforms for IoT: handle at the same time limited available resources, adaptive run-time behavior, and predictability. The presentation will introduce recent advances in this direction.

Thursday, June 11 : Efficiently Safe: Decoding the Dichotomy in Mixed-Criticality Systems
Prof. Arvind Easwaran
School of Computer Science and Engineering
Nanyang Technological University

Arvind Easwaran is an Associate Professor in the School of Computer Science and Engineering at Nanyang Technological University (NTU), Singapore. He received a PhD degree in Computer and Information Science from the University of Pennsylvania, USA, in 2008. Prior to joining NTU in 2013, he has been an Invited Research Scientist at the Polytechnic Institute of Porto, Portugal, between 2009 and 2010, and a Research & Development Scientist at Honeywell Aerospace, USA, between 2010 and 2012. He is a ACM Distinguished Speaker since 2018 and a Cluster Director in the Future Mobility Solutions research programme at the Energy Research Institute @ NTU.

Abstract: Real-time mixed-criticality systems have stringent timing requirements in the form of hard deadlines and a collection of tasks having different levels of importance or criticality hosted on a single hardware platform. Avionics and automotive are two well known domains for such systems, where the criticality level has a strong correlation with the assurance levels used for certification. Traditionally, static processor partitioning, in the form of fixed allocation of processing time, has been employed to ensure isolation between the different criticality tasks and guarantee task deadlines. However, due to increasing software and hardware complexity, determining a tight bound on the worst-case execution time of tasks is becoming increasingly difficult. As a result, pessimistic upper-bounds are often used for critical tasks, and this leads to a significant processor under-utilisation when used with static partitioning. To overcome this inefficiency, the concept of mixed-criticality scheduling has emerged in the last decade. Under this paradigm, processing capacity is partitioned among all the tasks using a less conservative execution time estimate. In the eventuality that some critical task requires additional execution, the schedule is adapted to favour the critical tasks over less critical ones.
In this talk, I will focus on both the theoretical as well as practical aspects of processor scheduling for real-time mixed-criticality systems. In the context of multiprocessors, I will present a fluid scheduling model and its extensions which have been shown to have an optimal processor speed-up bound of 4/3. In the context of uniprocessors, I will focus on the practical challenges of favouring critical tasks over the less critical ones, and present extensions to task and scheduling models that explore the trade-off between modelling complexity and system performance. Finally, I will also introduce an automotive test bed that was developed in NTU to specifically explore this trade-off.